// One-bit wide, N-bit long double shift register

module lab1_DoubleShiftReg 
#(parameter N=64)
(
    input clk_left,
    input clk_right,
    input direction, // 1 means shift_left
    input enable,
    input sr_in,
    output sr_out
);
    wire clk; 
    reg [N-1:0] sr; // Declare the shift register
    assign clk=(enable==1'b1)?((direction==1'b1)?clk_left:clk_right):1'b1;
    always @ (posedge clk)
    begin
        if (direction == 1'b1)  
            begin 
                sr[N-1:1] <= sr[N-2:0]; // shift left 
                sr[0] <= sr_in;
            end 
        else 
            begin 
            sr[N-2:0] <= sr[N-1:1]; // shift right 
            sr[N-1] <= sr_in;
            end 
    end
    assign sr_out = (enable==1'b1)?((direction==1'b1)?sr[N-1]:sr[0]):1'bZ;
    // Catch the outgoing bit
endmodule
